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CAT28C16A
16K-Bit CMOS PARALLEL E2PROM FEATURES
s Fast Read Access Times: 200 ns s Low Power CMOS Dissipation: s End of Write Detection: DATA Polling s Hardware Write Protection s CMOS and TTL Compatible I/O s 10,000 Program/Erase Cycles s 10 Year Data Retention s Commercial, Industrial and Automotive
-Active: 25 mA Max. -Standby: 100 A Max.
s Simple Write Operation:
-On-Chip Address and Data Latches -Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time: 10ms Max
Temperature Ranges
DESCRIPTION
The CAT28C16A is a fast, low power, 5V-only CMOS Parallel E2PROM organized as 2K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling signals the start and end of the self-timed write cycle. Additionally, the CAT28C16A features hardware write protection. The CAT28C16A is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 10,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 24-pin DIP and SOIC or 32-pin PLCC packages.
BLOCK DIAGRAM
A4-A10 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 2,048 x 8 E2PROM ARRAY
VCC
HIGH VOLTAGE GENERATOR
CE OE WE
CONTROL LOGIC I/O BUFFERS TIMER DATA POLLING I/O0-I/O7
A0-A3
ADDR. BUFFER & LATCHES
COLUMN DECODER
5089 FHD F02
(c) 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 25033-00 2/98
CAT28C16A
PIN CONFIGURATION
DIP Package (P)
A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 WE OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
SOIC Package (J,K)
A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 WE OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
PLCC Package (N)
VCC WE NC A7 NC NC NC
A6 A5 A4 A3 A2 A1 A0 NC I/O0
4 3 2 1 32 31 30 5 29 6 28 7 27 8 26 9 25 TOP VIEW 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20
I/O1 I/O2 I/O3 I/O4 VSS NC I/O5
A8 A9 NC NC OE A10 CE I/O7 I/O6
PIN FUNCTIONS
Pin Name A0-A10 I/O0-I/O7 CE OE WE VCC VSS NC Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable 5V Supply Ground No Connect
5089 FHD F01
MODE SELECTION Mode Read Byte Write (WE Controlled) Byte Write (CE Controlled) Standby, and Write Inhibit Read and Write Inhibit H X CE L L L X H WE H OE L H H X H I/O DOUT DIN DIN High-Z High-Z Power ACTIVE ACTIVE ACTIVE STANDBY ACTIVE
CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 5V Symbol CI/O(1) CIN(1) Test Input/Output Capacitance Input Capacitance Max. 10 6 Units pF pF Conditions VI/O = 0V VIN = 0V
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25033-00 2/98
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CAT28C16A
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on Any Pin with Respect to Ground(2) ........... -2.0V to +VCC + 2.0V VCC with Respect to Ground ............... -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND
(1)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Min. 10,000 10 2000 100
Max.
Units Cycles/Byte Years Volts mA
Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
TDR(1) VZAP
(1)
ILTH(1)(4)
D.C. OPERATING CHARACTERISTICS VCC = 5V 10%, unless otherwise specified. Limits Symbol ICC ICCC(5) ISB ISBC(6) ILI ILO VIH(6) VIL(5) VOH VOL VWI Parameter VCC Current (Operating, TTL) VCC Current (Operating, CMOS) VCC Current (Standby, TTL) VCC Current (Standby, CMOS) Input Leakage Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Write Inhibit Voltage 3.0 -10 -10 2 -0.3 2.4 0.4 Min. Typ. Max. 35 25 1 100 10 10 VCC +0.3 0.8 Units mA mA mA A A A V V V V V IOH = -400A IOL = 2.1mA Test Conditions CE = OE = VIL, f = 1/tRC min, All I/O's Open CE = OE = VILC, f = 1/tRC min, All I/O's Open CE = VIH, All I/O's Open CE = VIHC, All I/O's Open VIN = GND to VCC VOUT = GND to VCC, CE = VIH
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC +1V. (5) VILC = -0.3V to +0.3V. (6) VIHC = VCC -0.3V to VCC +0.3V.
Doc. No. 25033-00 2/98
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CAT28C16A
A.C. CHARACTERISTICS, Read Cycle VCC = 5V 10%, unless otherwise specified. 28C16A-20 Symbol tRC tCE tAA tOE tLZ(1) tOLZ(1) tHZ(1)(2) tOHZ(1)(2) tOH(1) Read Cycle Time CE Access Time Address Access Time OE Access Time CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output Output Hold from Address Change 0 0 0 55 55 Parameter Min. 200 200 200 80 Max. Units ns ns ns ns ns ns ns ns ns
Figure 1. A.C. Testing Input/Output Waveform(3)
2.4 V INPUT PULSE LEVELS 0.45 V 0.8 V 2.0 V REFERENCE POINTS
5089 FHD F03
Figure 2. A.C. Testing Load Circuit (example)
1.3V 1N914
3.3K DEVICE UNDER TEST OUT CL = 100 pF
CL INCLUDES JIG CAPACITANCE
5089 FHD F04
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. (3) Input rise and fall times (10% and 90%) < 10 ns.
Doc. No. 25033-00 2/98
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CAT28C16A
A.C. CHARACTERISTICS, Write Cycle VCC = 5V 10%, unless otherwise specified. 28C16A-20 Symbol tWC tAS tAH tCS tCH tCW(2) tOES tOEH tWP(2) tDS tDH tDL tINIT(1) Write Cycle Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time CE Pulse Time OE Setup Time OE Hold Time WE Pulse Width Data Setup Time Data Hold Time Data Latch Time Write Inhibit Period After Power-up 10 100 0 0 150 15 15 150 50 10 50 5 20 Parameter Min. Max. 10 Units ms ns ns ns ns ns ns ns ns ns ns ns ms
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) A write pulse of less than 20ns duration will not initiate a write cycle.
Doc. No. 25033-00 2/98
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CAT28C16A
DEVICE OPERATION
Read Data stored in the CAT28C16A is transferred to the data bus when WE is held high, and both OE and CE are held Figure 3. Read Cycle
tRC ADDRESS tCE CE tOE OE VIH WE tLZ tOLZ DATA OUT HIGH-Z tOH DATA VALID tAA
28C16A F05
low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment.
tOHZ tHZ DATA VALID
Figure 4. Byte Write Cycle [WE Controlled]
tWC ADDRESS tAS tCS CE tAH tCH
OE tOES WE tDL DATA OUT HIGH-Z tWP tOEH
DATA IN
DATA VALID tDS tDH
5089 FHD F06
Doc. No. 25033-00 2/98
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CAT28C16A
Byte Write A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms. Figure 5. Byte Write Cycle [CE Controlled]
ADDRESS tAS tAH tCW CE
DATA Polling DATA polling is provided to indicate the completion of a byte write cycle. Once a byte write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0-I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self-timed byte write cycle, all I/O's will output true data during a read cycle.
tWC
tDL
tOEH OE tCS WE HIGH-Z DATA OUT tOES tCH
DATA IN
DATA VALID tDS tDH
5089 FHD F07
Figure 6. DATA Polling
ADDRESS
CE
WE tOEH OE tWC I/O7 DIN = X DOUT = X DOUT = X tOE tOES
28C16A F08
Doc. No. 25033-00 2/98
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CAT28C16A
HARDWARE DATA PROTECTION The following is a list of hardware data protection features that are incorporated into the CAT28C16A. (1) VCC sense provides for write protection when VCC falls below 3.0V min. (2) A power on delay mechanism, tINIT (see AC characteristics), provides a 5 to 20 ms delay before a write sequence, after VCC has reached 3.0V min. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high. (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle.
ORDERING INFORMATION
Prefix CAT Device # 28C16A N Suffix I -20 T
Optional Company ID
Product Number
Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) A = Automotive (-40 to +105C)* Package P: PDIP N: PLCC J: SOIC (JEDEC) K: SOIC (EIAJ)
Tape & Reel T: 500/Reel
Speed 20: 200ns
* -40C to +125C is available upon request
28C16A F09
Notes: (1) The device used in the above example is a CAT28C16ANI-20T (PLCC, Industrial temperature, 200 ns Access Time, Tape & Reel).
Doc. No. 25033-00 2/98
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